ARM Assembly Language. Programming and Architecture.

Chapter 1: The History of ARM and Microcontrollers Section 1.1: Introduction to Microcontrollers Section 1.2: The ARM Family History Problems Answers to Review Questions Chapter 2: ARM Architecture and Assembly Language Programming Section 2.1: The General Purpose Registers in the ARM Section 2.2: The ARM Memory Map Section 2.3: Load and Store Instructions in ARM Section 2.4: ARM CPSR (Current Program Status Register) Section 2.5: ARM Data Format and Directives Section 2.6: Introduction to ARM Assembly Programming Section 2.7: Assembling an ARM Program Section 2.8: The Program Counter and Program ROM Space in the ARM Section 2.9: Some ARM Addressing Modes Section 2.10: RISC Architecture in ARM Section 2.11: Viewing Registers and Memory with ARM Keil IDE Problems Answers to Review Questions Chapter 3: Arithmetic and Logic Instructions and Programs Section 3.1: Arithmetic Instructions Section 3.2: Logic Instructions Section 3.3: Rotate and Barrel Shifter Section 3.4: Shift and Rotate Instructions in ARM Cortex (Case Study) Section 3.5: BCD and ASCII Conversion Problems Answers to Review Questions Chapter 4: Branch, Call, and Looping in ARM Section 4.1: Looping and Branch Instructions Section 4.2: Calling Subroutine with BL Section 4.3: ARM Time Delay and Instruction Pipeline Section 4.4: Conditional Execution Problems Answers to Review Questions Chapter 5: Signed Numbers and IEEE 754 Floating Point Section 5.1: Signed Numbers Concept Section 5.2: Signed Number Instructions and Operations Section 5.3: IEEE 754 Floating-Point Standards Problems: Answers to Review Questions Chapter 6: ARM Memory Map, Memory Access, and Stack Section 6.1: ARM Memory Map and Memory Access Section 6.2: Stack and Stack Usage in ARM Section 6.3: ARM Bit-Addressable Memory Region Section 6.4: Advanced Indexed Addressing Mode Section 6.5: ADR, LDR, and PC Relative Addressing Problems Answers to Review Questions Chapter 7: ARM Pipeline and CPU Evolution Section 7.1: ARM Pipeline Evolution Section 7.2: Other CPU Enhancements Problems Answers to Review Questions Appendix A: ARM Cortex-M3 Instruction Description Section A.1: List of ARM Cortex-M3 Instructions Section A.2: ARM Cortex-M3 Instruction Description Appendix B: ARM Assembler Directives Section B.1: List of ARM Assembler Directives Section B.2: Description of ARM Assembler Directives Appendix C: Macros What is a macro and how is it used? Macros vs. subroutines Appendix D: Flowcharts and Pseudocode Flowcharts Pseudocode Appendix E: Passing Arguments into Functions E.1: Passing arguments through registers E.2: Passing through memory using references E.3: Passing arguments through stack E.4: AAPCS (ARM Application Procedure Call Standard) Appendix F: ASCII Codes ADC Add with Carry ADCS Add with Carry (and update the flags) ADD ADD ADDS ADD and update the flags ADR Load PC-Relative Address AND Logical AND ANDS Logical AND (update flags) ASR Arithmetic Shift right ASRS Arithmetic Shift right (update the flags) B Branch (unconditional jump) Bxx Branch Conditional BFC Bit Field Clear BFI Bit Field Insert BIC Bit Clear BICS Bit Clear (update flags) BKPT Breakpoint BL Branch with Link (this is Call instruction) BLX Branch Indirect with Link BX Branch Indirect (BX LR is used for Return) CBNZ Compare and Branch on Non-Zero CBZ Compare and Branch on Zero CDP Coprocessor Data processing CLREX Clear Exclusive CLZ Count Leading Zero CMN Compare Negative CMP Compare CPSID Change processor ID and Disable Interrupt CPSIE Change Processor State and Enable Interrupt DMB Data Memory Barrier DSB Data Synchronization Barrier EOR Exclusive OR EORS Exclusive OR and update the flags ISB Instruction Synchronization Barrier IT If-Then Condition Block LDC Load Coprocessor LDM Load Multiple registers LDMDB Load Multiple registers and Decrement Before each access LDMEA Load Multiple registers from Empty Ascending LDMFD Load Multiple registers Full Descending LDMIA Load Multiple registers and Increment after each Access LDR Load Register LDR Rx,=Value Load Register with 32-bit value LDRB Load Register Byte LDRBT Load Register Byte with Translation LDREX, LDREXB, LDREXH Load Register Exclusive LDRH Load Register Halfword LDRSB Load Register signed Byte LDRSH Load Register Signed Halfword LDRT Load Register with Translation LSL Logical Shift Left LSLS Logical Shift Left (update the flags) LSR Logical Shift Right LSRS Logical Shift Right (update the flags) MCR Move to Coprocessor from ARM Register MLA Multiply Accumulate MLS Multiply and Subtract MOV Move (ARM7) MOV Move (ARM Cortex) MOVS Move (and update flags) MOVT Move Top MOVW Move 16-bit constant MRC Move to ARM Register from Coprocessor MRS Move to general Register from Special register MSR Move to Special register from general Register MUL Unsigned Multiplication MVN Move Negative MVNS Move Negative and update the flags NOP No Operation ORN Logical OR Not ORNS OR Not and update flags ORR Logical OR ORRS Logical OR and update the flags POP POP register from Stack PUSH PUSH register onto stack RBIT Reverse Bits REV Reverse byte order in a word RV16 Reverse byte order in 16-bit REVSH Reverse byte order in bottom halfword and sign extend ROR Rotate Right RORS Rotate Right (update the flags) RRX Rotate Right with extend RRXS Rotate Right with extend (update the flags) RSB Reverse Subtract RSBS Reverse Subtract and update the flags SBC Subtract with Carry (Borrow) SBCS Subtract with Carry (Borrow) and update the flags SBFX Sign Bit Field extract SDIV Signed Divide SEV Send Event SMLAL Signed Multiply Accumulate Long SMULL Signed Multiply Long SSAT Sign Saturate STM Store Multiple STMDB Store Multiple register and Decrement Before STMEA Store Multiple register Empty Ascending STMIA Store Multiple register Empty Ascending STMFD Store Multiple register Full Descending STR Store Register STRB Store Register Byte STRBT Store Register Byte with Translation STRD Store Register Double (two words) STREX, STREXB, STREXH Store Register Exclusive STRH Store Register Halfword STRT Store Register SUB Subtract SUBS Subtract SVC supervisor Call (Software Interrupt) SXTB Sign Extend byte SXTH Sign Extend Halfword TBB Table Branch Byte TBH Table Branch halfword TEQ Test Equivalence TST Test UBFX Unsigned Bit filed extract UDIV Unsigned Divide UMLAL Unsigned Multiply with Accumulate UMULL Unsigned Multiply Long USAT Unsigned Saturate UXBT Zero extend a byte UXTH Zero extend halfword WFE Wait for event WFI Wait for interrupt ALIGN AREA DCB directive (define constant byte) DCD directive (define constant word) DCW directive (define constant half-word) ENDP or ENDFUNC ENTRY EQU (Equate) EXPORT or GLOBAL EXTRN (External) FUNCTION or PROC INCLUDE RN (equate)