__CMOS PLL Synthesizers: Analysis and Design__ presents both fundamentals and state of the art PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, S D fractional-N synthesizer prototype is implemented in 0.35mm CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which elegantly tackle speed and integration bottlenecks of PLL synthesizer. This book is useful as a PLL synthesizer manual for both academic researchers and industry design engineers. The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage. Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented. It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes. An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering. The throughput of ADCs can be increased by using parallelism. This is demonstrated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. Circuit Techniques for Low-Voltage and High-Speed A/D Converters presents a total of seven prototypes: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO techniques. This monograph will prove to be a useful reference for both academics and professionals whom are active in the Analog Circuit Design and Communications field For four decades the evolution of integrated circuits has followed Moore's law, according to which the number of transistors per square millimeter of silicon doubles every 18 months. At the same time transistors have become faster, making possible ever-increasing clock rates in digital circuits. This trend seems set to continue for at least another decade without slowing down. Thus, in the near future the processing power of digital circuits will continue to increase at an accelerating pace. For analog circuits the evolution of technology is not as beneficial. Thus, there is a trend to move signal processing functions from the analog domain to the digital one, which, besides allowing for a higher level of accuracy, provides savings in power consumption and silicon area, increases robustness, speeds up the design process, brings flexibility and programmability, and increases the possibilities for design reuse. In many applications the input and output signals of the system are inherently analog, preventing all-digital realizations; at the very least a conversion between analog and digital is needed at the - terfaces. Typically, moving the analog-digital boundary closer to the outside world increases the bit rate across it. In telecommunications systems the trend to boost bit rates is based on - ploying widerbandwidths and a higher signal-to-noise ratio. At the same time radio architectures in many applications are evolving toward software-defined radio, one of the main characteristics of which is the shifting of the anal- digital boundary closer to the antenna. Thanks to the advance of semiconductor and communication technology, the wireless communication market has been booming in the last two decades. It evolved from simple pagers to emerging third-generation (3G) cellular phones. In the meanwhile, broadband communication market has also gained a rapid growth. As the market always demands hi- performance and low-cost products, circuit designers are seeking hi- integration communication devices in cheap CMOS technology. The phase-locked loop frequency synthesizer is a critical component in communication devices. It works as a local oscillator for frequency translation and channel selection in wireless transceivers and broadband cable tuners. It also plays an important role as the clock synthesizer for data converters in the analog-and-digital signal interface. This book covers the design and analysis of PLL synthesizers. It includes both fundamentals and a review of the state-of-the-art techniques. The transient analysis of the third-order charge-pump PLL reveals its locking behavior accurately. The behavioral-level simulation of PLL further clarifies its stability limit. Design examples are given to clearly illustrate the design procedure of PLL synthesizers. A complete derivation of reference spurs in the charge-pump PLL is also presented in this book. The in-depth investigation of the digital CA modulator for fractional-N synthesizers provides insightful design guidelines for this important block.
cmos Circuit Design For Rf Sensors Is About Cmos Circuit Design For Sensor And Actuators To Be Used In Wireless Rf Systems. The Main Application Is Implantable Transducers For Biomedical Purposes Such As Sensing Of Nerve Signals And Electrical Stimulation Of Nerves. Special Focus Is Put On The Power And Data Link In A Wireless System With Transducers Which Are Powered Via The Rf Link. Novel Principles And Methods Are Presented For The Regulation Of Power To The Sensors And For The Distribution Of Data And Power In An Implanted Transducer System. One Of The Main Problems In Such Systems Is The Transmission Of Power Via An Rf Link. This Problem Is Analyzed In Detail And Solutions Incorporating An Rf Magnetic Link To The Transducers Are Identified. The Theoretical Results Are Supported By Experiments From Cmos Chips Including A System Chip For Functional Electrical Stimulation (fes). The Work Shows That A System On Chip (soc) Solution Is Feasible Using Cmos Technology For The Rf Sensors. The Only Components Which Cannot Be Integrated On The Chip Are The Antenna Coil And A Capacitor For Energy Storage.
cmos Circuit Design For Rf Sensors Will Be A Useful Reference For Academics As Well As Research Scientists Whom Are Active In The Field Of (analog) Circuit Design And Sensors.
design Of High-performance Cmos Voltage-controlled Oscillators Presents A Phase Noise Modeling Framework For Cmos Ring Oscillators. The Analysis Considers Both Linear And Nonlinear Operation. It Indicates That Fast Rail-to-rail Switching Has To Be Achieved To Minimize Phase Noise. Additionally, In Conventional Design The Flicker Noise In The Bias Circuit Can Potentially Dominate The Phase Noise At Low Offset Frequencies. Therefore, For Narrow Bandwidth Plls, Noise Up Conversion For The Bias Circuits Should Be Minimized. We Define The Effective Q Factor (qeff) For Ring Oscillators And Predict Its Increase For Cmos Processes With Smaller Feature Sizes. Our Phase Noise Analysis Is Validated Via Simulation And Measurement Results.
the Digital Switching Noise Coupled Through The Power Supply And Substrate Is Usually The Dominant Source Of Clock Jitter. Improving The Supply And Substrate Noise Immunity Of A Pll Is A Challenging Job In Hostile Environments Such As A Microprocessor Chip Where Millions Of Digital Gates Are Present.
"CMOS PLL Synthesizers : Analysis and Design presents both fundamentals and state-of-the-art PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis is given. A 16mW, 2.4GHz, sub-2V, S D fractional-N synthesizer prototype is implemented in 0.35mm CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance multiplier, which tackle speed and integration bottlenecks of PLL synthesizers." "This book is useful as a PLL synthesizer manual for both academic researchers and industry design engineers."--Résumé de l'éditeur "CMOS PLL Synthesizers: Analysis and Design presents both fundamentals and state-of-the-art PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis is given. A 16mW, 2.4GHz, sub-2V, S D fractional-N synthesizer prototype is implemented in 0.35mm CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance multiplier, which tackle speed and integration bottlenecks of PLL synthesizers." "This book is useful as a PLL synthesizer manual for both academic researchers and industry design engineers."--BOOK JACKET This book presents both fundamentals and the state of the art of PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, Sigma Delta fractional-N synthesizer prototype is implemented in 0.35m m CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which tackle speed and integration bottlenecks of PLL synthesizer elegantly.This book is conceived as a PLL synthesizer manual for both academia researchers and industry design engineers. "The primary audience for Design of High-Performance CMOS Voltage-Controlled Oscillators is research workers and design engineers who concentrate on high performance communication circuits. This work will also be of interest to analog circuit designers."--BOOK JACKET. In the last decade, the rapid growth of wireless applications has led to an increasing demand of fully integrated, low-cost, low-power, and high-performance transceivers. By Mikko E. Waltari And Kari A.i. Halonen. Includes Bibliographical References (p. 239-254). Keliu Shu, Edgar Sánchez-sinencio. Includes Bibliographical References And Index.
