Linear CMOS RF Power Amplifiers : a Complete Design Workflow

The work establishes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focuses on design guidelines of the inductor’s geometrical characteristics for power applications and covers their measurement and characterization. Additionally, a model is proposed which would facilitate designs in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers limitations that CMOS processes can impose on implementation. The book also provides different techniques and architectures that allow for optimization. Preface Contents Acronyms 1 Introduction Abstract The Power Amplifier Impact of PA on Integrated Transceivers Requirements of Modern Wireless Standards Effect of the Communication Range Effect of the PAPR in Digital Multicarrier Modulation Schemes CMOS Technology Organization of the Book References 2 Power Amplifier Fundamentals: Metrics Abstract AM--AM DistortionAM--AM distortion Saturated PowerSaturated power and One dB Compression PointOne dB compression point Third Order Intercept PointThird-order intercept point AM--PM DistortionAM-PM distortion Digital Channel Metrics Spectral RegrowthSpectral regrowth Adjacent Channel Leakage Ratio Spectrum Emission Mask Error Vector Magnitude EfficiencyEfficiency Metrics Drain EfficiencyDrain efficiency Power-Added EfficiencyPower-added efficiency Power Back-OffPower back-off Transmit Power Levels StabilityStability Power CapabilityPower capability Conclusions References 3 Power Amplifier Fundamentals: Classes Abstract Current Source PAs Transconductance ModelTransconductance model Knee VoltageKnee voltage Class AClass A power amplifier PAs Class ABClass AB power amplifier PAs Class BClass B power amplifier PAs Class CClass C power amplifier PAs Summary Switch-Type PAs Class DClass D power amplifier PAs Class EClass E power amplifier PAs Harmonic Tuning: Class F PAs Conclusions References 4 CMOS Performance Issues Abstract Low Supply VoltageSupply voltage Effect of the Knee VoltageKnee voltage Load TransformationLoad Transformation ReliabilityReliability Issues Oxide BreakdownOxide breakdown Hot Carrier DegradationHot carrier degradation Reliability Projection Reliability Under RF Stress Transistor ParasiticsTransistor Parasitics SubstrateSubstrate Issues StabilityStability Issues Conclusions References 5 Enhancement TechniquesEnhancement techniques for CMOS Linear PAs Abstract CascodeCascode power amplifier PAs Thick Oxide CascodeCascode power amplifierthick oxide cascode PAs Self-Biased CascodeCascode power amplifierself-biased cascode PAs Multiple Stacked CascodeCascode power amplifiermultiple stacked cascode PAs Combined PAs Integrated Transformer Power CombiningIntegrated transformer power combining Simple Parallel CombinationSimple parallel combination Doherty PAsDoherty power amplifier Predistorted PAPredistorted power amplifiers Dynamic SupplyDynamic supply or Envelope TrackingEnvelope tracking Adaptive BiasingAdaptive biasing Conclusions References 6 Power Amplifier Design Abstract A Model for the Power Amplifier Model Description Linear RegionLinear Region Nonlinear RegionNonlinear Region Output Power, Drain Efficiency and PAE Model-Based Analyses Effect of the Cascode TransistorCascode transistor Effect of the Inductor Parasitics Effect of PA Biasing Starting Point Parameters Measurement Comparisons Power Amplifier Design Schematic Circuit Description Design Flow Output Matching NetworkOutput matching network Output StageOutput stage Input Matching NetworkInput matching network Driver StageDriver stage Interstage MatchingInterstage matching and Stability Power InductorPower inductor Design Top Metal Layer Width Considerations Multiple Metal Layer Considerations Inductor GeometryInductor geometry Considerations Accuracy Analysis of the Electromagnetic Simulator Power InductorPower inductor Design Flow LayoutLayout Design Circuit Isolation Differential Design Considerations Balanced Inductors Common-CentroidCommon-centroid Passive Components Low Value Resistors RF Capacitors Stage Isolation PadPad Design Conclusions References 7 Test Setups and Results Abstract Equipment Inductor Characterization Test SetupTest Setup Prior Steps PlanarizationPlanarization SkatingSkating Cleaning Calibration De-EmbeddingDe-Embedding Results PA Characterization Single-Tone TestTest SetupSingle-Tone Tests Test SetupTest Setup Input Matching and GainPower Gain Output P1dB and PSAT Current Consumption Power-Added EfficiencyPower-Added Efficiency StabilityStability Digital Channel TestTest SetupDigital Channel Tests Test SetupTest Setup Spectrum Emission MaskSpectrum Emission Mask Error Vector MagnitudeError Vector Magnitude ReliabilityReliability and Maximum Rating Conclusions References 8 Conclusion Abstract Highlights Main Contributions A Complete Design Flow for a CMOS Linear PA Useful Enhancement Techniques for Linear CMOS PAs Design and Characterization of Power Inductors Index This work describes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focus on design guidelines for the inductor's geometrical characteristics for power applications and cover their measurement and characterization. Additionally, a model is proposed which facilitates design in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers the limitations that CMOS processes can impose on implementation. The book also details various techniques and architectures that allow for optimization This work describes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focus on design guidelines for the inductor s geometrical characteristics for power applications and cover their measurement and characterization. Additionally, a model is proposed which facilitates design in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers the limitations that CMOS processes can impose on implementation. The book also details various techniques and architectures that allow for optimization