Modeling Microprocessor Performance

__Modeling Microprocessor Performance__ focuses on the development of a design and evaluation tool, named RIPE (Rensselaer Interconnect Performance Estimator). This tool analyzes the impact on wireability, clock frequency, power dissipation, and the reliability of single chip CMOS microprocessors as a function of interconnect, device, circuit, design and architectural parameters. It can accurately predict the overall performance of existing microprocessor systems. For the three major microprocessor architectures, DEC, PowerPC and Intel, the results have shown agreement within 10% on key parameters. The models cover a broad range of issues that relate to the implementation and performance of single chip CMOS microprocessors. The book contains a detailed discussion of the various models and the underlying assumptions based on actual design practices. As such, RIPE and its models provide an insightful tool into single chip microprocessor design and its performance aspects. At the same time, it provides design and process engineers with the capability to model, evaluate, compare and optimize single chip microprocessor systems using advanced technology and design techniques at an early design stage without costly and time consuming implementation. RIPE and its models demonstrate the factors which must be considered when estimating tradeoffs in device and interconnect technology and architecture design on microprocessor performance. Front Matter....Pages i-xvii Introduction....Pages 1-16 System Level Representation....Pages 17-25 Interconnect Parameters....Pages 27-51 Transistor Count And Area Models....Pages 53-90 System Wireability....Pages 91-124 Device Parameters....Pages 125-133 Cycle Time Estimation Model....Pages 135-153 System Power Dissipation....Pages 155-174 Microprocessor Performance Evaluation....Pages 175-192 Back Matter....Pages 193-195