Power Electronics and Design 2004

Книга Power Electronics and Design 2004 Power Electronics and Design 2004Книги Электротехника и связь Автор: Kluwer Ultra Год издания: 2004 Формат: pdf Издат.:Kluwer Academic Publishers Размер: 5.28 ISBN: 1-4020-8076-X Язык: Английский0 (голосов: 0) Оценка:Todaywearebeginningtohavetofaceuptotheconsequencesofthe stunning success of Moore’s Law, that astute observation by Intel’s Gordon Moore which predicts that integrated circuit transistor densities will double every12to18months.Thisobservationhasnowheldtrueforthelast25 yearsormore,andtherearemanyindicationsthatitwillcontinuetohold trueformanyyearstocome.Thisbookappearsatatimewhenthefirst examples ofcomplex circuitsin65nmCMOS technology are beginning to appear,andtheseproductsalreadymusttakeadvantageofmanyofthe techniques to be discussed and developed in this book. So why then should ourincreasingsuccessatminiaturization,asevidencedbythesuccessof Moore’s Law, be creating so many new difficulties in power management in circuit designs? Contents......Page 6 Contributors......Page 8 Preface......Page 10 Introduction......Page 14 1.1 INTRODUCTION......Page 18 1.2 POWER CONSUMPTION BECOMES CRITICAL......Page 19 1.3 TRADITIONAL APPROACHES TO POWER REDUCTION......Page 21 1.4 ZERO-VTH DEVICES......Page 22 1.5 DESIGN APPROACHES TO POWER REDUCTION......Page 27 Acknowledgement......Page 35 References......Page 36 2.1 INTRODUCTION......Page 38 2.2 OPTICAL INTERCONNECT TECHNOLOGY......Page 39 2.3 AN OPTICAL CLOCK DISTRIBUTION NETWORK......Page 40 2.4 QUANTITATIVE POWER COMPARISON BETWEEN ELECTRICAL AND OPTICAL CLOCK DISTRIBUTION NETWORKS......Page 46 2.5 OPTICAL NETWORK ON CHIP......Page 50 References......Page 55 3.1 INTRODUCTION......Page 57 3.2 SINGLE ELECTRONICS......Page 58 3.3 MOLECULAR ELECTRONICS......Page 68 3.4 DISCUSSION......Page 69 References......Page 70 4.1 INTRODUCTION......Page 73 4.2 LEAKAGE MODEL AND CHARACTERISTICS......Page 77 4.3 SUBTHRESHOLD LEAKAGE REDUCTION......Page 78 4.4 LEAKAGE REDUCTION METHOD FOR BOTH SUBTHRESHOLD AND GATE LEAKAGE CURRENT......Page 84 4.5 RESULTS......Page 91 4.6 CONCLUSIONS......Page 98 References......Page 99 5.1 INTRODUCTION......Page 101 5.2 BACKGROUND......Page 103 5.3 PARTITIONED SHARED MEMORY ARCHITECTURE......Page 106 5.4 PERFORMANCE AND ENERGY CHARACTERIZATION......Page 108 5.5 EXPLORATION FRAMEWORK......Page 112 5.6 EXPERIMENTAL RESULTS......Page 114 5.7 CONCLUSIONS......Page 117 References......Page 118 6.1 INTRODUCTION......Page 120 6.2 BACKGROUND – TUNABLE CACHE PARAMETERS......Page 121 6.3 A SELF-TUNING LEVEL ONE CACHE ARCHITECTURE......Page 122 6.4 AUTOMATIC TUNING OF A TWO-LEVEL CACHE ARCHITECTURE - THE TCAT......Page 126 6.5 USING A VICTIM BUFFER IN AN APPLICATION SPECIFIC MEMORY HEIRARCHY......Page 130 6.6 LOW STATIC-POWER FREQUENT-VALUE DATA CACHES......Page 133 References......Page 138 7. REDUCING ENERGY CONSUMPTION IN CHIP MULTIPROCESSORS USING WORKLOAD VARIATIONS......Page 140 7.1 INTRODUCTION......Page 141 7.2 CHIP MULTIPROCESSOR ARCHITECTURE AND EXECUTION MODEL......Page 143 7.3 LOAD IMBALANCE IN PARALLEL EXECUTION......Page 144 7.4 COMPILER SUPPORT......Page 147 7.5 ADDITIONAL OPTIMIZATIONS......Page 149 7.6 EXPERIMENTS......Page 151 References......Page 155 8.1 INTRODUCTION......Page 158 8.2 ENERGY EFFICIENT HETEROGENEOUS SOC’S......Page 160 8.3 ULTRA LOW POWER COMPONENTS......Page 163 8.4 DESIGN & ARCHITECTURE EXPLORATION......Page 166 8.5 DOMAIN-SPECIFIC CO DESIGN ENVIRONMENTS......Page 167 References......Page 171 9.1 INTRODUCTION......Page 173 9.2 TRANSFORMATIONS OVERVIEW......Page 174 9.3 METHODOLOGY......Page 176 9.4 CASE STUDIES......Page 178 9.5 EXPERIMENTAL RESULTS......Page 186 9.6 CONCLUSIONS......Page 187 References......Page 188 10.1 INTRODUCTION......Page 189 10.2 PRELIMINARIES......Page 190 10.3 BACKLIGHT AND TRANSMITTANCE SCALING......Page 202 References......Page 213 11.1 INTRODUCTION......Page 215 11.2 REMOTE STORAGE SPACE......Page 216 11.3 SWAP DEVICES......Page 217 11.4 EXPERIMENTAL SETUP......Page 219 11.5 CHARACTERIZATION OF SWAPPING COSTS......Page 220 11.6 POWER OPTIMIZATION......Page 221 11.7 CASE STUDY......Page 225 11.8 CONCLUSION......Page 227 References......Page 228 12.1 INTRODUCTION......Page 231 12.2 PHYSICAL LAYER......Page 232 12.3 SYSTEM INTERCONNECT ARCHITECTURE......Page 234 12.4 DATA LINK LAYER......Page 236 12.5 NETWORK LAYER......Page 238 12.6 TRANSPORT LAYER......Page 240 12.7 SYSTEM AND APPLICATION LAYERS......Page 242 12.8 APPLICATION-SPECIFIC NETWORKS-ON-CHIP......Page 243 12.9 CONCLUSIONS......Page 247 References......Page 248 13. SYSTEM LEVEL POWER MODELING AND SIMULATION OF HIGH-END INDUSTRIAL NETWORK-ON-CHIP......Page 250 13.2 BACKGROUND......Page 251 13.3 ON-CHIP NETWORK: STBUS INTERCONNECT......Page 252 13.4 ENABLING ENERGY EXPLORATION FOR NOC......Page 253 13.5 STBUS ENERGY MODEL......Page 257 13.6 OPTIMAL DESIGN OF EXPERIMENTS......Page 258 13.7 STBUS POWER MODEL VALIDATION AND EXPERIMENTAL RESULTS......Page 261 13.8 LOW EFFORT, HIGH ACCURACY POWER MACRO MODELING......Page 265 13.9 CONCLUSIONS......Page 269 References......Page 270 14. ENERGY-AWARE ADAPTATIONS FOR END-TO-END VIDEOSTREAMINGTOMOBILEHANDHELD DEVICES......Page 272 14.1 MOTIVATION......Page 273 14.2 RELATED WORK......Page 274 14.3 SYSTEM MODEL......Page 277 14.4 HARDWARE/ARCHITECTURAL LEVEL OPTIMIZATIONS......Page 278 14.5 OS/MIDDLEWARE LEVEL OPTIMIZATIONS......Page 281 14.6 APPLICATION LAYER ADAPTATION......Page 286 14.7 SUMMARY......Page 287 References......Page 288 Power consumption is a key limitation in many high-speed and high-data-rate electronic systems today, ranging from mobile telecom to portable and desktop computing systems, especially when moving to nanometer technologies. Ultra Low-Power Electronics and Design offers to the reader the unique opportunity of accessing in an easy and integrated fashion a mix of tutorial material and advanced research results, contributed by leading scientists from academia and industry, covering the most hot and up-to-date issues in the field of the design of ultra low-power devices, systems and applications. "Ultra Low-Power Electronics and Design offers to the reader the unique opportunity of accessing a mix of tutorial material and advanced research results, contributed by leading scientists from academia and industry, covering the most hot and up-to-date issues in the field of the design of ultra low-power devices, systems and applications."--BOOK JACKET.