SAT-Based Scalable Formal Verification Solutions (Series on Integrated Circuits and Systems)

Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors. __SAT-Based Scalable Formal Verification__ Solutions discusses in detail several of the latest and interesting scalable SAT-based techniques including: Hybrid SAT Solver, Customized Bounded/Unbounded Model Checking, Distributed Model Checking, Proofs and Proof-based Abstraction Methods, Verification of Embedded Memory System & Multi-clock Systems, and Synthesis for Verification Paradigm. These techniques have been designed and implemented in a verification platform Verisol (formally called DiVer) and have been used successfully in industry. This book provides algorithmic details and engineering insights into devising scalable approaches for an effective realization. It also includes the authors’ practical experiences and recommendations in verifying the large industry designs using VeriSol. The book is primarily written for researchers, scientists, and verification engineers who would like to gain an in-depth understanding of scalable SAT-based verification techniques. The book will also be of interest for CAD tool developers who would like to incorporate various SAT-based advanced techniques in their products.

Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors.

SAT-Based Scalable Formal Verification Solutions discusses in detail several of the latest and interesting scalable SAT-based techniques including: Hybrid SAT Solver, Customized Bounded/Unbounded Model Checking, Distributed Model Checking, Proofs and Proof-based Abstraction Methods, Verification of Embedded Memory System & Multi-clock Systems, and Synthesis for Verification Paradigm. These techniques have been designed and implemented in a verification platform Verisol (formally called DiVer) and have been used successfully in industry. This book provides algorithmic details and engineering insights into devising scalable approaches for an effective realization. It also includes the authors’ practical experiences and recommendations in verifying the large industry designs using VeriSol.

The book is primarily written for researchers, scientists, and verification engineers who would like to gain an in-depth understanding of scalable SAT-based verification techniques. The book will also be of interest for CAD tool developers who would like to incorporate various SAT-based advanced techniques in their products.

Front Matter....Pages i-xxix Design Verification Challenges....Pages 1-16 Background....Pages 17-40 Front Matter....Pages 41-41 Efficient Boolean Representation....Pages 43-62 Hybrid DPLL-Style SAT Solver....Pages 63-76 Front Matter....Pages 77-77 SAT-Based Bounded Model Checking....Pages 79-112 Distributed SAT-Based BMC....Pages 113-129 Efficient Memory Modeling in BMC....Pages 131-153 BMC for Multi-Clock Systems....Pages 155-171 Front Matter....Pages 173-173 Proof by Induction....Pages 175-183 Unbounded Model Checking....Pages 185-212 Front Matter....Pages 213-213 Proof-Based Iterative Abstraction....Pages 215-243 Front Matter....Pages 245-245 SAT-Based Verification Framework....Pages 247-261 Synthesis for Verification....Pages 263-295 Back Matter....Pages 297-326 This book provides an engineering insight into how to provide a scalable and robust verification solution with ever increasing design complexity and sizes. It describes SAT-based model checking approaches and gives engineering details on what makes model checking practical. The book brings together the various SAT-based scalable emerging technologies and techniques covered can be synergistically combined into a scalable solution.