Symbolic Model Checking

Formal verification means having a mathematical model of a system, a language for specifying desired properties of the system in a concise, comprehensible and unambiguous way, and a method of proof to verify that the specified properties are satisfied. When the method of proof is carried out substantially by machine, we speak of automatic verification. __Symbolic Model Checking__ deals with methods of automatic verification as applied to computer hardware. The practical motivation for study in this area is the high and increasing cost of correcting design errors in VLSI technologies. There is a growing demand for design methodologies that can yield correct designs on the first fabrication run. Moreover, design errors that are discovered before fabrication can also be quite costly, in terms of engineering effort required to correct the error, and the resulting impact on development schedules. Aside from pure cost considerations, there is also a need on the theoretical side to provide a sound mathematical basis for the design of computer systems, especially in areas that have received little theoretical attention. Front Matter....Pages i-xvii Introduction....Pages 1-9 Model Checking....Pages 11-24 Symbolic Model Checking....Pages 25-60 The SMV System....Pages 61-85 A Distributed Cache Protocol....Pages 87-112 Mu-Calculus Model Checking....Pages 113-128 Induction and Model Checking....Pages 129-141 Equivalence Computations....Pages 143-151 A Partial Order Approach....Pages 153-177 Conclusion....Pages 179-181 Back Matter....Pages 183-194