Test Pattern Generation using Boolean Proof Engines

After producing a chip, the functional correctness of the integrated circuit has to be checked. Otherwise products with malfunctions would be delivered to customers, which is not acceptable for any company. Many algorithms for "Automatic Test Pattern Generation" (ATPG) have been proposed in the last 30 years. But due to the ever increasing design complexity, new techniques have to be developed that can cope with today’s circuits. While classical approaches are based on backtracking on the circuit structure, several approaches based on "Boolean Satisfiability" (SAT) have been proposed since the early 80s. In __Test Pattern Generation using Boolean Proof Engines__, we give an introduction to ATPG. The basic concept and classical ATPG algorithms are reviewed. Then, the formulation as a SAT problem is considered. As the underlying engine, modern SAT solvers and their use on circuit related problems are comprehensively discussed. Advanced techniques for SAT-based ATPG are introduced and evaluated in the context of an industrial environment. The chapters of the book cover efficient instance generation, encoding of multiple-valued logic, usage of various fault models, and detailed experiments on multi-million gate designs. The book describes the state of the art in the field, highlights research aspects, and shows directions for future work. Front Matter....Pages i-xii Introduction....Pages 1-8 Preliminaries....Pages 9-28 Boolean Satisfiability....Pages 29-42 SAT-Based ATPG....Pages 43-52 Learning Techniques....Pages 53-70 Multiple-Valued Logic....Pages 71-87 Improved Circuit-to-CNF Conversion....Pages 89-111 Branching Strategies....Pages 113-117 Integration into Industrial Flow....Pages 119-135 Delay Faults....Pages 137-171 Summary and Outlook....Pages 173-175 Back Matter....Pages 177-192 Gives an introduction to ATPG. This work reviews the basic concept and classical ATPG algorithms. It also considers the formulation as a SAT problem. It covers efficient instance generation, encoding of multiple-valued logic, usage of various fault models, and detailed experiments on multi-million gate designs