Three-dimensional Integrated Circuit Design (Systems on Silicon)

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance. Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to enhance dramatically chip performance and functionality, while reducing the distance among devices on a chip. They promise solutions to the current "interconnect bottleneck" challenges faced by IC designers. They also may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of three-dimensional integrated circuits. * Demonstrates how to overcome "Interconnect Bottleneck" with 3D Integrated Circuit Design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers.* The FIRST book on 3D Integrated Circuit Design...provides up-to-date information that is otherwise difficult to find;* Focuses on design issues key to the product development cyle...good design plays a major role in exploiting the implementation flexibilities offered in the third dimension;* Provides broad coverage of 3D IC Design, including Interconnect Prediction Models, Thermal Management Techniques, and Timing Optimization...offers practical view of designing 3D circuits. Cover Page......Page 1 Copyright......Page 2 Dedication......Page 3 Perface......Page 4 Acknowledgments......Page 6 Introduction......Page 7 From the Integrated Circuit to the Computer......Page 8 Interconnects, an Old Friend......Page 11 Three-Dimensional or Vertical Integration......Page 14 Opportunities for Three-Dimensional Integration......Page 15 Technological/Manufacturing Limitations......Page 17 Interconnect Design......Page 18 Book Organization......Page 19 Three-Dimensional Integration......Page 23 Three-Dimensional Integrated Circuits......Page 24 System-on-Package......Page 25 Wire-Bonded System-in-Package......Page 30 Peripheral Vertical Interconnects......Page 32 Area Array Vertical Interconnects......Page 34 Metallizing the Walls of an SiP......Page 36 Cost Issues for 3-D Integrated Systems......Page 38 Summary......Page 41 3-D Integrated Circuit Fabrication Technologies......Page 43 Stacked 3-D ICs......Page 44 Laser Crystallization......Page 45 Seed Crystallization......Page 47 Other Fabrication Techniques for Stacked 3-D ICs......Page 50 3-D Fin-FETs......Page 52 3-D ICs with Through Silicon (TSV) or Interplane Vias......Page 54 Capacitively Coupled 3-D ICs......Page 59 Inductively Coupled 3-D ICs......Page 61 Vertical Interconnects for 3-D ICs......Page 62 Electrical Characteristics of Through Silicon Vias......Page 67 Summary......Page 69 Interconnect Prediction Models......Page 70 Interconnect Prediction Models for 2-D Circuits......Page 71 Interconnect Prediction Models for 3-D ICs......Page 74 Projections for 3-D ICs......Page 78 Summary......Page 82 Floorplanning Techniques......Page 84 Single-versus Multistep Floorplanning for 3-D ICs......Page 86 Multi-Objective Floorplanning Techniques for 3-D ICs......Page 89 Placement Techniques......Page 92 Multi-Objective Placement for 3-D ICs......Page 93 Routing Techniques......Page 97 Layout Tools......Page 100 Summary......Page 102 Thermal Management Techniques......Page 104 Thermal Analysis of 3-D ICs......Page 105 Closed-Form Temperature Expressions......Page 106 Compact Thermal Models......Page 113 Mesh-Based Thermal Models......Page 115 Thermal-Driven Floorplanning......Page 116 Thermal-Driven Placement......Page 122 Thermal Management Techniques Employing Thermal Vias......Page 125 Region-Constrained Thermal Via Insertion......Page 126 Thermal Via Planning Techniques......Page 129 Thermal Wire Insertion......Page 135 Summary......Page 136 Timing Optimization for Two-Terminal Interconnects......Page 139 Interplane Interconnect Models......Page 140 Elmore Delay Model of an Interplane Interconnect......Page 145 Interplane Interconnect Delay......Page 147 Optimum Via Location......Page 149 Improvement in Interconnect Delay......Page 152 Two-Terminal Interconnects with Multiple-Interplane Vias......Page 155 Two-Terminal Via Placement Heuristic......Page 159 Two-Terminal Via Placement Algorithm......Page 163 Application of the Via Placement Technique......Page 164 Summary......Page 171 Timing-Driven Via Placement for Interplane Interconnect Trees......Page 173 Interconnect Trees......Page 177 Single Critical Sink Interconnect Trees......Page 178 Interconnect Tree Via Placement Algorithm (ITVPA)......Page 180 Via Placement Results and Discussion......Page 181 Summary......Page 187 3-D Circuit Architectures......Page 189 Classification of Wire-Limited 3-D Circuits......Page 190 Three-Dimensional Microprocessors and Memories......Page 191 Three-Dimensional Microprocessor Logic Blocks......Page 193 Three-Dimensional Design of Cache Memories......Page 194 Architecting a 3-D Microprocessor - Memory System......Page 199 Three-Dimensional Networks-on-Chip......Page 201 3-D NoC Topologies......Page 202 Zero-Load Latency for 3-D NoC......Page 204 Power Consumption in 3-D NoC......Page 208 Performance and Power Analysis for 3-D NoC......Page 210 Parameters of 3-D Networks-on-Chip......Page 211 2-D IC-3-D NoC......Page 213 3-D IC - 2-D NoC......Page 215 3-D IC - 3-D NoC......Page 218 Power Consumption in 3-D NoC......Page 220 3-D IC - 2-D NoC......Page 221 3-D IC - 3-D NoC......Page 222 Design Aids for 3-D NoCs......Page 225 3-D NoC Simulator......Page 226 Evaluation of 3-D NoCs under Different Traffic Scenarios......Page 229 Three-Dimensional FPGAs......Page 235 Design Aids for 3-D FPGAs......Page 242 Summary......Page 248 Case Study: Clock Distribution Networks for 3-D ICs......Page 251 MIT Lincoln Laboratories 3-D IC Fabrication Technology......Page 252 3-D Circuit Architecture......Page 257 Clock Signal Distribution in 3-D Circuits......Page 261 Timing Characteristics of Synchronous Circuits......Page 262 Clock Distribution Network Structures within the Test Circuit......Page 265 Experimental Results......Page 269 Summary......Page 276 Conclusions......Page 278 Enumeration of Gate Pairs in a 3-D IC......Page 281 Formal Proof of Optimum Single Via Placement......Page 283 Proof of the Two-Terminal Via Placement Heuristic......Page 284 Proof of Condition for Via Placement of Multiterminal Nets......Page 288 References......Page 290 D......Page 305 M......Page 306 S......Page 307 T......Page 308 W......Page 309 With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. Connecting effectively (interconnect design) all of these chip elements has become the greatest determining factor in overall performance. 3-D integrated circuit design may offer the best solutions in the near future.

This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of 3-D integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of 3-D integrated circuits.

* Demonstrates how to overcome "interconnect bottleneck" with 3-D integrated circuit design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers
* The FIRST book on 3-D integrated circuit design...provides up-to-date information that is otherwise difficult to find
* Focuses on design issues key to the product development cycle...good design plays a major role in exploiting the implementation flexibilities offered in the 3-D
* Provides broad coverage of 3-D integrated circuit design, including interconnect prediction models, thermal management techniques, and timing optimization...offers practical view of designing 3-D circuits Deals with 3-D integrated circuit design, covering the technological and design aspects of this design paradigm. This book proposes effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits.