Timing

With the advent of nanometer technologies, circuit performance constraints are becoming ever more stringent. In this context, automated timing analysis and optimization becomes imperative for the design of high-performance circuits that must satisfy a demanding set of constraints. Timing overviews the state of the art in timing analysis and optimization, and is intended to serve as a compendium that can provide an introduction to the uninitiated reader, as a ready reference for a practitioner, or as a source for the accomplished researcher. A comprehensive overview of the basics of timing analysis is provided, and this is augmented with techniques that incorporate physical effects arising in deep submicron and nanometer technologies. The book provides an in-depth treatment of the analysis of interconnect systems, static timing analysis for combinational circuits, timing analysis for sequential circuits, and timing optimization techniques at the transistor and layout levels. The intended audience includes CAD tool developers, graduate students, research professionals, and the merely curious. 01......Page 1 02......Page 9 03......Page 12 04......Page 40 05......Page 78 06......Page 104 07......Page 120 08......Page 140 09......Page 158 10......Page 187 11......Page 213 12......Page 255 13......Page 265 7 TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS 7.1 INTRODUCTION A general sequential circuit is a network of computational nodes (gates) and memory elements (registers).