Transactions on High-Performance Embedded Architectures and Compilers V (Lecture Notes in Computer Science, 11225)

Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This 5th issue contains extended versions of papers by the best paper award candidates of IC-SAMOS 2009 and the SAMOS 2009 Workshop, colocated events of the 9th International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS 2009, held in Samos, Greece, in 2009. The 7 papers included in this volume were carefully reviewed and selected. The papers cover research on embedded processor hardware/software design and integration and present challenging research trends. Guest Editorial 6 Special Issue on SAMOS 2009 International Symposium on Systems, Architectures, Modeling, and Simulation 6 LNCS Transactions on High-Performance Embedded Architectures and Compilers 8 Contents 9 Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards 10 1 Introduction and Related Work 10 2 Architecture 12 3 Mapping Methodology 13 3.1 Memory Access 14 3.2 Compute-Bound Kernels 15 3.3 Memory-Bound Kernels 16 3.4 Configuration Space Exploration 16 3.5 Double Buffering Support 17 4 Multiresolution Filtering 18 5 Results 21 6 Conclusions 27 References 28 Programmable and Scalable Architecture for Graphics Processing Units 30 1 Introduction 30 2 Related Work 32 3 TTAGPU Architecture 33 3.1 Transport Triggered Architectures 34 3.2 TTA Vs. SPMD 35 3.3 Scheduling a Real Shader 38 4 Software Graphics Pipeline 39 5 Results 41 5.1 Instruction Level Scalability of the Graphics Pipeline 41 5.2 Comparison Against a Real GPU 42 6 Conclusions 45 References 45 Circular Buffers with Multiple Overlapping Windows for Cyclic Task Graphs 48 1 Introduction 48 2 Related Work 52 3 Input Applications 52 4 Inter-task Communication Between Multiple Producers and Consumers 53 5 Multiple Overlapping Windows in a Circular Buffer 55 5.1 A Circular Buffer with a Sliding Read and Write Window 55 5.2 A Circular Buffer with an Overlapping Read and Write Window 57 5.3 A Circular Buffer with Multiple Overlapping Windows 59 6 Insertion of Communication and Synchronization Statements 60 7 Case Study 63 8 Conclusion 65 References 66 A Hardware-Accelerated Estimation-Based Power Profiling Unit - Enabling Early Power-Aware Embedded Software Design and On-Chip Power Management 68 1 Introduction 68 2 Related Work 70 2.1 Measurement-Based Methods 70 2.2 Estimation-Based Methods 70 3 Contributions 72 4 Design of a Hardware-Accelerated Estimation-Based Power Profiling Unit 73 4.1 Power Model 73 4.2 Power Characterization Process 74 4.3 Power Estimation Architecture 75 4.4 Design Flow 76 4.5 System Set-Up 77 5 Case Study: Profiling of Power-Critical Smart-Card Applications 78 5.1 Smart-Card Architecture Overview 78 5.2 Payment Application Profile Analysis 80 5.3 Accuracy of Estimation-Based Power Profiling 83 5.4 Performance Evaluation 83 5.5 Resource Allocation 84 6 Concept for Estimation-Based On-Chip Power Management 85 7 Conclusions and Future Work 86 References 86 The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors 88 1 Introduction 88 2 The ACOTES Stream Compiler 89 3 Stream Programming and acolib 91 4 ASM Machine Description 92 5 ASM Program Description 95 6 Platform Characterisation 99 7 Validation 101 8 Using the ASM 101 9 Related Work 104 10 Conclusions 105 References 106 Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability 109 1 Introduction 109 2 Architecture Overview 111 2.1 Run-Time Configurable Scratchpad 111 2.2 Virtualized User-Level DMA 112 2.3 Interprocessor Communication (IPC) Primitives 113 3 FPGA-Based Prototype and Implementation 114 3.1 Configurable Cache/Scratchpad Memory 115 3.2 NI Operation and Mechanisms 116 4 Hardware Cost, Latency and Software Evaluation 122 4.1 Design Cost in FPGA Resources 122 4.2 Area Benefits of Integrated Cache/NI Controller 122 4.3 End-to-End Latency 123 4.4 Case Studies: Software Use of Hardware Primitives 125 5 Related Work 127 6 Conclusions and Future Work 127 References 128 A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design 130 1 Introduction 130 2 Related Work 132 3 Multistage Networks 133 3.1 Dynamic Placement and Routing 136 4 Super-VLIW Architecture 138 5 Experimental Results 142 6 Conclusions 146 References 147 Author Index 149 Front Matter ....Pages I-IX Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards (Richard Membarth, Hritam Dutta, Frank Hannig, Jürgen Teich)....Pages 1-20 Programmable and Scalable Architecture for Graphics Processing Units (Carlos S. de La Lama, Pekka Jääskeläinen, Heikki Kultala, Jarmo Takala)....Pages 21-38 Circular Buffers with Multiple Overlapping Windows for Cyclic Task Graphs (Tjerk Bijlsma, Marco J. G. Bekooij, Gerard J. M. Smit)....Pages 39-58 A Hardware-Accelerated Estimation-Based Power Profiling Unit - Enabling Early Power-Aware Embedded Software Design and On-Chip Power Management (Andreas Genser, Christian Bachmann, Christian Steger, Reinhold Weiss, Josef Haid)....Pages 59-78 The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors (Paul M. Carpenter, Alex Ramirez, Eduard Ayguade)....Pages 79-99 Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability (George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis Kavadias, Xiaojun Yang, Dionisios Pnevmatikatos et al.)....Pages 100-120 A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design (Ricardo Ferreira, Cristoferson Bueno, Marcone Laure, Monica Pereira, Luigi Carro)....Pages 121-139 Back Matter ....Pages 141-141