Multi-Processor System-on-Chip 2 : Applications

A Multi-Processor System-on-Chip (MPSoC) is the key component for complex applications. These applications put huge pressure on memory, communication devices and computing units. This book, presented in two volumes – Architectures and Applications – therefore celebrates the 20th anniversary of MPSoC, an interdisciplinary forum that focuses on multi-core and multi-processor hardware and software systems. It is this interdisciplinarity which has led to MPSoC bringing together experts in these fields from around the world, over the last two decades. Multi-Processor System-on-Chip 2 covers application-specific MPSoC design, including compilers and architecture exploration. This second volume describes optimization methods, tools to optimize and port specific applications on MPSoC architectures. Details on compilation, power consumption and wireless communication are also presented, as well as examples of modeling frameworks and CAD tools. Explanations of specific platforms for automotive and real-time computing are also included. Cover 1 Half-Title Page 3 Dedication 4 Title Page 5 Copyright Page 6 Contents 7 Foreword 13 Acknowledgments 15 PART 1: MPSoC for Telecom 17 1 From Challenges to Hardware Requirements for Wireless Communications Reaching 6G 19 1.1. Introduction 20 1.2. Breadth of workloads 22 1.2.1. Vision, trends and applications 22 1.2.2. Standard specifications 24 1.2.3. Outcome of workloads 29 1.3. GFDM algorithm breakdown 30 1.3.1. Equation 31 1.3.2. Dataflow processing graph and matrix representation 31 1.3.3. Pseudo-code 32 1.4. Algorithm precision requirements and considerations 34 1.5. Implementation 37 1.5.1. Implementation considerations 39 1.5.2. Design space exploration 39 1.5.3. Measurements for low-end and high-end use cases 42 1.6. Conclusion 44 1.7. Acknowledgments 45 1.8. References 45 2 Towards Tbit/s Wireless Communication Baseband Processing: When Shannon meets Moore 49 2.1. Introduction 50 2.2. Role of microelectronics 52 2.3. Towards 1 Tbit/s throughput decoders 53 2.3.1. Turbo decoder 55 2.3.2. LDPC decoder 57 2.3.3. Polar decoder 57 2.4. Conclusion 59 2.5. Acknowledgments 59 2.6. References 59 PART 2: Application-specific MPSoC Architectures 63 3 Automation for Industry 4.0 by using Secure LoRaWAN Edge Gateways 65 3.1. Introduction 66 3.2. Security in IIoT 68 3.3. LoRaWAN security in IIoT 69 3.4. Threat model 71 3.4.1. LoRaWAN attack model 71 3.4.2. IIoT node attack model 72 3.5. Trusted boot chain with STM32MP1 73 3.5.1. Trust base of node 73 3.5.2. Trusted firmware in STM32MP1 73 3.5.3. Trusted execution environments and OP-TEE 74 3.5.4. OP-TEE scheduling considerations 76 3.5.5. OP-TEE memory management 76 3.5.6. OP-TEE client API 77 3.5.7. TEE internal core API 78 3.5.8. Root and chain of trust 78 3.5.9. Hardware unique key 78 3.5.10. Secure clock 79 3.5.11. Cryptographic operations 79 3.6. LoRaWAN gateway with STM32MP1 80 3.7. Discussion and future scope 81 3.8. Acknowledgments 82 3.9. References 82 4 Accelerating Virtualized Distributed NVMe Storage in Hardware 85 4.1. Introduction 86 4.1.1. Virtualization and traditional hypervisors 87 4.1.2. Hyperconverged versus disaggregated cloud architectures 88 4.1.3. NVMe flash storage 90 4.2. Motivation: NVMe storage for the cloud 91 4.2.1. Motivation for a new hypervisor 91 4.2.2. Motivation for accelerating disaggregated storage 92 4.3. Design 93 4.3.1. Optimizing the hypervisor I/O operations 93 4.3.2. Design of accelerated disaggregated storage 96 4.4. Implementation 102 4.4.1. The NexVisor platform 103 4.4.2. Accelerated disaggregated storage 103 4.5. Results 106 4.5.1. Sequential reads 106 4.5.2. Sequential writes 106 4.5.3. Sequential reads on one NVMe drive 108 4.5.4. Network performance 108 4.6. Conclusion 109 4.7. References 109 5 Modular and Open Platform for Future Automotive Computing Environment 111 5.1. Introduction 112 5.2. Outline of this approach 114 5.2.1. Centralized computation, distributed data 114 5.2.2. Modularity and heterogeneity 115 5.2.3. Tools for specification, configuration and integration 117 5.3. Results 118 5.3.1. Hardware platform 119 5.3.2. FACE SW architecture 124 5.3.3. FACE Tool Suite 128 5.4. Use case 132 5.4.1. Adaptive braking system 132 5.5. Conclusion 134 5.6. References 135 6 Post-Moore Datacenter Server Architecture 139 6.1. Introduction 140 6.2. Background: today’s blades are from the desktops of the 1980s 141 6.3. Memory-centric server design 143 6.4. Data management accelerators 145 6.5. Integrated network controllers 146 6.6. References 147 PART 3: Architecture Examples and Tools for MPSoC 151 7 SESAM: A Comprehensive Framework for Cyber–Physical System Prototyping 153 7.1. Introduction 154 7.2. An overview of the SESAM platform 154 7.2.1. Multi-abstraction system prototyping 155 7.2.2. Assessing extra-functional system properties 156 7.3. VPSim: fast and easy virtual prototyping 156 7.3.1. Writing peripherals in Python 157 7.3.2. The ModelProvider interface 158 7.3.3. QEMU support 160 7.3.4. Online simulation monitoring 162 7.3.5. Acceleration methods 162 7.4. Hybrid prototyping 163 7.4.1. Co-simulation mode 164 7.4.2. Co-emulation mode 165 7.4.3. Runtime performance analysis and debugging features 165 7.5. FMI for co-simulation 166 7.5.1. Functional mock-up interface 167 7.5.2. VPSim integration in FMI co-simulation 168 7.6. Conclusion 171 7.7. References 171 8 StaccatoLab: A Programming and Execution Model for Large-scale Dataflow Computing 173 8.1. Introduction 174 8.2. Static dataflow 177 8.2.1. Synchronous dataflow 178 8.2.2. Cyclo-static dataflow 182 8.2.3. Dataflow graph transformations 183 8.3. Dynamic dataflow 184 8.3.1. Data-dependent dataflow 184 8.3.2. Non-determinate dataflow 188 8.4. Dataflow execution models 191 8.4.1. A brief review of dataflow theory 191 8.4.2. The StaccatoLab execution model 193 8.5. StaccatoLab 196 8.5.1. Dataflow graph description and analysis 196 8.5.2. Verilog synthesis 196 8.6. Large-scale dataflow computing? 198 8.6.1. What kind of applications? 198 8.6.2. Why effective? 199 8.6.3. Why efficient? 200 8.7. Acknowledgments 201 8.8. References 201 9 Smart Cameras and MPSoCs 205 9.1. Introduction 205 9.2. Early VLSI video processors 206 9.3. Video signal processors 207 9.4. Accelerators 209 9.5. From VSP to MPSoC 211 9.6. Graphics processing units 213 9.7. Neural networks and tensor processing units 213 9.8. Conclusion 215 9.9. References 215 10. Software Compilation and Optimization Techniques for Heterogeneous Multi-core Platforms 219 10.1. Introduction 220 10.2. Dataflow modeling 223 10.2.1. General concepts 223 10.2.2. Process networks 224 10.2.3. C for process networks 225 10.3. Source-to-source-based compiler infrastructure 230 10.3.1. Design rationale 230 10.3.2. Implementation strategy 232 10.4. Software distribution 234 10.4.1. KPN analysis 235 10.4.2. Static KPN mapping 236 10.4.3. Hybrid KPN mapping 237 10.5. Results 238 10.5.1. Applications and experiences 238 10.5.2. Retargetability 245 10.6. Conclusion 246 10.7. References 247 List of Authors 253 Author Biographies 257 Index 267 EULA 269